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Juried Engineering CD4011BE CD4011B CD4011 CMOS Quad 2-Input NAN

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The CD4011B Quad 2 Input NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates
Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V
Buffered inputs and outputs, 100% tested for quiescent current at 20 V
Standardized symmetrical output characteristics, 5-V, 10-V, and 15-V parametric ratings, Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of "B" Series CMOS Devices"
Maximum input current of 1 ÂµA at 18 V over-full package temperature range; 100 nA at 18 V and 25Â°C, Noise margin (over full package temperature range: 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 at VDD = 15 V

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Product description

The CD4011B Quad 2 Input NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.